This invention relates to clock data recovery circuitry. More particularly, this invention relates to providing clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable parts per million (PPM) detector.
An increasingly important type of signaling between devices is signaling in which the clock signal information is embedded in a serial data stream so that no separate clock signal needs to be transmitted. For example, data may be transmitted serially in “packets” of several successive serial data words preceded by a serial “header” that includes several training bits having a predetermined pattern of binary ones and zeros. The clock signal information is embedded in the data signal by the high-to-low and/or low-to-high transitions in that signal, which must have at least one high-to-low or low-to-high transition within a certain number of clock signal cycles. At the receiver the clock signal is “recovered” from the data signal. The clock signal is then used to recover the data from the data signal. For convenience herein this general type of signaling will be referred to generically as “clock data recovery” or “CDR” signaling.
CDR signaling is now being used in many different signaling protocols. These protocols vary with respect to such parameters as clock signal frequency, header configuration, packet size, data word length, number of parallel channels, etc. Such signaling protocols include (1) industry-standard forms such as XAUI, InfiniBand (IB), Fibre Channel (FC), Gigabit Ethernet, Packet Over SONET or POS-5, Serial RapidIO, etc., and (2) any of a wide range of non-industry-standard or “custom” forms that particular users devise for their own uses. Such custom protocols often have at least some features similar to industry-standard protocols, but deviate from industry standards in other respects.
A programmable logic device (“PLD”) is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. Rather than having to design and build separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those various logic tasks. Many manufacturers of electronic circuitry and systems find PLDs to be an advantageous way to provide various components of what they need to produce.
CDR signaling is an area in which it would be highly desirable to have the ability to use PLDs to avoid having to always design and build CDR circuitry (e.g., receivers) that are specific to each of the many different CDR protocols.
CDR circuitry is typically designed to run at a fixed data rate for a given protocol. As a result, support for a different data rate may be complicated and may require the CDR circuitry to be reset and reprogrammed with a different configuration. In view of the foregoing, it would be desirable to provide CDR circuitry that can operate at a fixed data rate for a given protocol and that can also adapt to changing data rates caused by the interfacing of different protocols.
CDR circuitry often includes a parts per million (PPM) detector (or frequency detector) that computes a frequency difference between a reference clock signal and a recovered clock signal produced by the CDR circuitry. The PPM detector, which usually has a fixed PPM setting (e.g., 100 PPM or 200 PPM), outputs a signal when the PPM detector detects a frequency difference that is at or within the fixed PPM setting. In some embodiments, the fixed PPM setting may be too small or too large to be effective due to, for example, different system requirements, different types of applications implemented on the system, varying reference clock frequencies associated with different protocols, and process variations. In view of the foregoing, it would further be desirable to provide CDR circuitry with a dynamically adjustable PPM detector.